AT A GLANCE
- Cryogenic Boost: IBM presents groundbreaking CMOS transistors designed for liquid-nitrogen cooling at the IEEE International Electron Device Meeting, doubling performance at 77 K.
- Nanosheet Revolution: IBM’s nanosheet transistors, replacing FinFET tech, allow 50 billion transistors in a small space, featured in the 2-nanometer prototype processor.
- Performance Surge: Operating at 77 K doubles device performance, offering less charge carrier scattering, lower power, faster electron movement, and enhanced sensitivity between “on” and “off” states.
- Power Efficiency: Lowering power consumption through reduced voltage changes, achieved by cooling to 77 K, potentially enables chip size reduction by scaling down transistor width.
- Threshold Voltage Challenge: Overcoming threshold voltage increase at lower temperatures, IBM adopts a novel approach with dual metal gates and dual dipoles to enhance efficiency in CMOS technology.
- Efficient Dipole Integration: IBM engineers CMOS chips with paired n-type and p-type transistors, introducing metal impurities to form dipoles, reducing energy needs for electron movement and enhancing transistor efficiency.
IBM Unveils Breakthrough in Cryogenic Electronics at IEDM 2023
In a groundbreaking development, IBM researchers showcased a pioneering CMOS transistor designed specifically for liquid-nitrogen cooling at the 2023 IEEE International Electron Device Meeting (IEDM) in San Francisco this December.
Nanosheet Technology Revolutionizes Transistor Design
The new nanosheet transistors, which employ a channel-splitting technique using thin silicon sheets, are revolutionizing transistor design. According to Ruqiang Bao, a senior researcher at IBM, this nanosheet architecture allows for the accommodation of an astonishing 50 billion transistors within the space of a fingernail. These transistors, set to replace the current FinFET technology, are integral to IBM’s first 2-nanometer prototype processor. The combination of nanosheet technology and liquid-nitrogen cooling holds the promise of enhancing overall performance.
Cryogenic Cooling Doubles Device Performance
The IBM researchers discovered that operating the nanosheet transistors at 77 kelvins (−196 °C) doubled device performance compared to standard room temperature conditions (300 K). The advantages of low-temperature systems include reduced charge carrier scattering and lower power consumption.
Enhancing Electron Mobility and Lowering Power Consumption
At cryogenic temperatures, the reduction in charge carrier scattering results in lower resistance in the wires, facilitating quicker electron movement through the device. The combination of lower power consumption and reduced scattering enables devices to drive a higher current at a given voltage.
Improved Sensitivity and Lower Power Consumption
Cooling the transistor to 77 K also enhances sensitivity between the device’s “on” and “off” positions, requiring a smaller change in voltage to switch states. This significant reduction in power consumption is particularly noteworthy. Lowering the power supply could lead to a reduction in chip size by decreasing the transistor width.
Addressing Threshold Voltage Challenges
However, challenges arise in lowering the threshold voltage—the voltage required to create a conducting channel between the source and drain or switch to the “on” position. Confronting this obstacle, the IBM researchers adopted a novel approach involving the integration of two different metal gates and dual dipoles.
Innovative Approach to Lowering Threshold Voltage
In CMOS technologies, which consist of pairs of n-type and p-type transistors, the researchers engineered their chips to form dipoles at the interface of both transistor types. This was achieved by introducing different metal impurities to each type, effectively lowering the energy needed to move electrons across the band edge. The result is a more efficient and groundbreaking transistor design.
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Source(s): IEEE Spectrum
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